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n umicro m ini51 ? de series datasheet may 22, 2014 page 1 of 70 revision 1.01 numicro m ini51 ? de series datasheet arm cortex ? -m0 32- bit microcontroller numicro mini51 ? de series datasheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro tm microcontroller based system design. nuvoton assumes no resp onsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvoton.com
n umicro m ini51 ? de series datasheet may 22, 2014 page 2 of 70 revision 1.01 numicro m ini51 ? de series datasheet table of contents 1 general description ................................................................................................. 7 2 features ........................................................................................... 8 3 abbreviations ................................................................................. 12 4 parts information list and pin configuration .............................. 13 numicro mini51 ? series selection code .......................................................... 13 4.1 numicro mini51 ? series product selection guide ............................................... 14 4.2 pin configuration ............................................................................... 15 4.3 4.3.1 lqfp 48 - pin .................................................................................................... 15 4.3.2 qfn 33- pin ................................................................................................................................ 16 4.3.3 tssop 20 - pin ............................................................................................................................ 17 4.3.4 mini 54fhc (tssop20 - pin) ........................................................................................................ 17 pin description ......................................................................................... 18 4.4 5 block diagram ................................................................................ 22 numicro mini51? block diagram ................................................................... 22 5.1 6 functional description ............................................................................ 23 memory organization ................................................................................. 23 6.1 6.1.1 overview .................................................................................................................................... 23 6.1.2 system memory map ................................................................................................................. 23 nested vectored interrupt controller (nvic) ...................................................... 24 6.2 6.2.1 overview .................................................................................................................................... 24 6.2.2 features ..................................................................................................................................... 24 6.2.3 exceptio n model and system interrupt map ............................................................................... 25 6.2.4 vector table .............................................................................................................................. 26 6.2.5 operation description ................................................................................................................ 27 system manager ....................................................................................... 28 6.3 6.3.1 overview .................................................................................................................................... 28 6.3.2 system reset ............................................................................................................................ 28 6.3.3 system power architecture ........................................................................................................ 28 6.3.4 whole system memory mapping ............................................................................................... 30 clock controller ........................................................................................ 31 6.4 6.4.1 overview .................................................................................................................................... 31 6.4.2 system clock and systick clock ............................................................................................... 32 6.4.3 isp clock source selection ....................................................................................................... 33
n umicro m ini51 ? de series datasheet may 22, 2014 page 3 of 70 revision 1.01 numicro m ini51 ? de series datasheet 6.4.4 module clock source selection ................................................................................................. 33 6.4.5 power - down mode clock ........................................................................................................... 34 6.4.6 frequency divider output .......................................................................................................... 34 analog comparator (acmp) ......................................................................... 36 6.5 6.5.1 overview .................................................................................................................................... 36 6.5.2 features ..................................................................................................................................... 36 analog - to - digital converter (adc) .................................................................. 37 6.6 6.6.1 overview .................................................................................................................................... 37 6.6.2 features ..................................................................................................................................... 37 flash mem ory controller (fmc) ..................................................................... 38 6.7 6.7.1 overview .................................................................................................................................... 38 6.7.2 features ..................................................................................................................................... 38 general purpose i/o (gpio) ......................................................................... 39 6.8 6.8.1 overview .................................................................................................................................... 39 6.8.2 features ..................................................................................................................................... 39 i2c serial interface controller (i2c) ................................................................ 40 6.9 6.9.1 overview .................................................................................................................................... 40 6.9.2 features ..................................................................................................................................... 40 enhanced pw m generator ........................................................................... 41 6.10 6.10.1 overview .................................................................................................................................... 41 6.10.2 features ..................................................................................................................................... 41 serial peripheral interface (spi) ..................................................................... 43 6.11 6.11.1 overview .................................................................................................................................... 43 6.11.2 features ..................................................................................................................................... 43 timer controller (tmr) ............................................................................... 44 6.12 6.12.1 overview .................................................................................................................................... 44 6.12.2 features ..................................................................................................................................... 44 uart controller (uart) ............................................................................. 45 6.13 6.13.1 overview .................................................................................................................................... 45 6.13.2 features ..................................................................................................................................... 45 watchdo g timer (wdt) ............................................................................... 46 6.14 6.14.1 overview .................................................................................................................................... 46 6.14.2 features ..................................................................................................................................... 46 7 arm? corte x? - m0 core ........................................................................ 47 overview ................................................................................................. 47 7.1
n umicro m ini51 ? de series datasheet may 22, 2014 page 4 of 70 revision 1.01 numicro m ini51 ? de series datasheet features ................................................................................................. 47 7.2 system timer (systick) .............................................................................. 48 7.3 8 application circuit ......................................................................... 49 9 mini51xxde electrical characteristics ......................................... 50 absolute maximum ratings .......................................................................... 50 9.1 dc electrical characteristics ......................................................................... 50 9.2 ac electrical characteristics ......................................................................... 58 9.3 9.3.1 external input clock ................................................................................................................... 58 9.3.2 external 4~24 mhz high speed crystal (hxt) ........................................................................... 58 9.3.3 typical crystal application circuits ............................................................................................ 59 9.3.4 22.1184 mhz internal high speed rc oscillator (hirc) ............................................................ 59 9.3.5 10 khz internal low speed rc oscillator(lirc) ........................................................................ 60 analog characteristics ................................................................................ 61 9.4 9.4.1 10- bit saradc .......................................................................................................................... 61 9.4.2 ldo & power management ....................................................................................................... 62 9.4.3 low voltage reset ..................................................................................................................... 62 9.4.4 brown - out detector .................................................................................................................... 63 9.4.5 power - on reset ......................................................................................................................... 63 9.4.6 comparator ................................................................................................................................ 64 flash dc electrical characteristics ................................................................. 65 9.5 10 package dimensions ........................................................................ 66 48- pin lqfp ............................................................................................ 66 10.1 33- pin qfn (4 mm x 4 mm) .......................................................................... 67 10.2 33- pin qfn (5 mm x 5 mm) .......................................................................... 68 10.3 20- pin tssop .......................................................................................... 69 10.4 11 revision history ....................................................................................................... 70
n umicro m ini51 ? de series datasheet may 22, 2014 page 5 of 70 revision 1.01 numicro m ini51 ? de series datasheet list of figures figure 4.1 - 1 numicro mini51 ? series selection code ................................................................ 13 figure 4.3 - 1 numicro mini51 ? series lqfp 48 - pin diagram ...................................................... 15 figure 4.3 - 2 numicro mini51 ? series qfn 33 - pin diagram ........................................................ 16 figure 4.3 - 3 numicro m ini 51 ? series tssop 20- pin diagram ................................................... 17 figure 4.3 - 4 numicro m ini 51 ? series tssop 20 - pin diagram ................................................... 17 figure 5.1 - 1 numicro mini51 ? series block diagram ................................................................. 22 figure 6.3 - 1 numicro mini51 ? series power architecture diagram ............................................ 29 figure 6.4 - 1 clock generator block diagram .............................................................................. 31 figure 6.4 - 2 system clock block diagram .................................................................................. 32 figure 6.4 - 3 systick clock control block diagram ..................................................................... 32 figure 6.4 - 4 ahb clock source for hclk ................................................................................... 33 figure 6.4 - 5 peripherals clock source selection for pclk ......................................................... 33 figure 6.4 - 6 clock source of frequency divider ......................................................................... 35 figure 6.4 - 7 block diagram of frequency divider ....................................................................... 35 figure 7.1 - 1 functional block diagram ....................................................................................... 47 figure 9 - 1mini5xde typical crystal application circuit ............................................................... 59 figure 9 - 2power - up ramp condition .......................................................................................... 64
n umicro m ini51 ? de series datasheet may 22, 2014 page 6 of 70 revision 1.01 numicro m ini51 ? de series datasheet list of tables table 4.1 - 1 list of abbreviations ................................................................................................. 12 table 4.2 - 1numicro mini51 ? series product selection guide .................................................... 14 table 6.1 - 1 address space assignments for on - chip modules .................................................. 23 table 6.2 - 1 exception model ....................................................................................................... 25 table 6.2 - 2 system interrupt map vector table .......................................................................... 26 table 6.2 - 3 vector table format ................................................................................................. 26 table 6.3 - 1 memory mapping table ............................................................................................ 30 table 6.4 - 1 peripheral clock source selection table ................................................................. 34
n umicro m ini51 ? de series datasheet may 22, 2014 page 7 of 70 revision 1.01 numicro m ini51 ? de series datasheet 1 general description the numicro m ini 51? series 32 - bit microcontroller is embedded with arm ? cortex? - m0 core for industrial control and applications which require high performance, high integration , and low cost. the cortex? - m0 is the newest arm ? embedded processor with 32 - bit performance at a cost equivalent to the traditional 8 - bit microcontroller. the numicro m ini 51? series can run up t o 24 mhz and operat e at 2.5v ~ 5.5v, - 40 ~ 105 , and t hus can afford to support a variety of industrial control and applications which need high cpu performance. the numicro m ini 51? series offers 4k/8k/16k - byte s embedded program flash, size configurable data flash (shared with program flash), 2 k - byte flash for the isp, and 2 k - byte sram . many system level peripheral functions , such as i / o port , ti mer, uart, spi, i 2 c, pwm, adc , watchdog timer , analog c omparator and brown - out d etector, have been incorporated into the numicro m ini 51? series in order to reduce component count, board space and system cost. these useful functions ma ke the numicro m ini 51? series powerful f or a wide range of application s. additionally, t he numicro m ini 51? series is equipped with isp ( i n - s ystem p rogramming) and icp (in - circuit programming) functions, which allow the user to update the program memory without removing the chip from the actual end product .
n umicro m ini51 ? de series datasheet may 22, 2014 page 8 of 70 revision 1.01 numicro m ini51 ? de series datasheet 2 features ? core ? arm ? cortex? - m0 core run ning up to 24 mhz ? one 24 - bit system timer ? supports l ow p ower sleep m ode ? a s ingle - cycle 32 - bit hardware multiplier ? nvic for the 32 interrupt inputs, each with 4 - level of priority ? supports serial wire debug (swd) interface and two watch points / four breakpoints ? b uilt - in ldo for w ide o perating v oltage r ange d : 2. 5 v to 5.5 v ? m emory ? 4 kb/ 8 k b / 16 k b f lash memory for program memory (aprom) ? configurable f lash memory for data memory ( data flash ) ? 2 k b f lash for loader (ldrom) ? 2 k b sram for internal scratch - pad ram (sram) ? clock control ? programmable system clock source ? s witch clock sources on - the - fly ? 4 ~ 24 mhz external crystal input (hxt) ? 32.768 khz external crystal input (lxt) for power - down wake - up and system operation clock ? 22 .1184 mhz internal oscillator (hirc) ( 1% accuracy at 25 o c, 5v ) ? dynamic ally calibrating the hirc osc to 22. 1184 mhz 1% from - 40 o c to 105 o c by external 32.768k crystal oscillator (lxt) ? 10 k hz internal l ow - power oscillator (lirc) for w atchdog timer and power - down wake - up ? i/o port ? up to 30 g eneral - p urpose i/o (gpio ) pins for lqfp - 48 package ? four i/o modes: ? input - only with high impendence ? push - p ull output ? open - d rain output ? quasi - bidirectional ? ttl/sch mitt trigger input select able ? i/o pin can be configured as interrup t source with edge/level setting ? supports h igh driver and high sink i / o mode ? configurable default i/o mode of all pins after por ? timer
n umicro m ini51 ? de series datasheet may 22, 2014 page 9 of 70 revision 1.01 numicro m ini51 ? de series datasheet ? provides t wo channel 32- bit timers . one 8 - bit pre - scale counter with 24 - bit up counter for each timer ? independent clock source for each timer ? p rovides o ne - shot, p eriodic, t oggle and c ontinuous operation modes ? 24- bit up counter value is readable through tdr (timer data register) ? provides trigger counting/free counting/counter reset function triggered by ext ernal capture pin or internal comparator signal ? provides event counter function ? supports w ake - up from idle or power - down mode ? wdt ( watch dog timer ) ? multiple clock sources ? supports w ake - up from idle or power - down mode ? interrupt or reset selectable on watchdog t ime - out ? pwm ? independ ent 1 6 - bit pwm duty control units with maximum six outputs ? supports group/synchronous/ independent / complementary modes ? supports one - shot or auto - reload mode ? support s edge - aligned and center - aligned type ? programmable dead - zone insertio n between complementary channels ? each output has independent polarity setting control ? hardware fault brake protection s ? supports duty, period, and fault break interrupts ? support s duty/period trigger adc conversion ? t imer comparing matching event trig ger pwm to do phase change ? support s comparator event trigger pwm to force pwm output low for current period ? p rovide s interrupt accumulation function ? uart (universal asynchronous receiver/transmitters) ? one uart device ? buffered receiver and transmitter , each with 1 6 - byte fifo ? optional f low control function (c ts n and rtsn) ? support s irda (sir) function ? programmable baud - rate generator up to 1/16 system clock ? support s rs - 485 function ? spi (serial peripheral interface) ? one spi devices ? supports master/slave mode
n umicro m ini51 ? de series datasheet may 22, 2014 page 10 of 70 revision 1.01 numicro m ini51 ? de series datasheet ? full - duplex synchronous serial data transfer ? provides 3 - wire function ? variable length of transfer data from 8 to 32 bits ? msb or lsb first data transfer ? rx latching data can be either at rising edge or at falling edge of serial clock ? tx sending data can be either at rising edge or at falling edge of serial clock ? supports byte suspend mode in 32 - bit transmission ? 4 - level depth fifo buffe r ? i 2 c ? support s master/slave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allow s devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handsh ake mechanism to suspend and resume serial transfer ? programmable clocks allow for versatile rate control ? supports 7 - bit addressing mode ? s upport s multiple address recognition ( four slave address es with mask option) ? s upport s power - down wake - up function ? support fifo function ? adc (analog - to - digital converter) ? 10- bit sar adc with 300k sps ? up to 8 - ch single - end input and one internal input from band - gap ? conversion start ed either by software trigger , pwm trigger, or external pin trigger ? supports conversion value monitoring (or comparison) for threshold voltage detectio n ? analog comparator ? two analog comparators with programmable 16 - level internal voltage reference ? build - in crv ( comparator reference voltage) ? s upport s hysteresis functio n ? interrupt when compared results changed ? isp ( in - system programming) and icp ( in - circuit programming) ? bod (brown - o ut detecto r ) ? with 4 p rogrammable threshold levels: 4.4v/ 3. 7 v/2.7v/2. 2 v
n umicro m ini51 ? de series datasheet may 22, 2014 page 11 of 70 revision 1.01 numicro m ini51 ? de series datasheet ? supports brown - out i nterrupt and r eset option ? 96- bit unique id ? lvr (low v oltage reset) ? threshold voltage level: 2.0v ? operating temperature: - 40~ 105 ? reliability : eft > 4kv, esd hbm pass 4kv ? packages: ? green package (rohs) ? 48- pin lqfp (7x7), 33- pin qfn (5x5) , 33- pin qfn ( 4 x 4 ) , 20- pin tssop
n umicro m ini51 ? de series datasheet may 22, 2014 page 12 of 70 revision 1.01 numicro m ini51 ? de series datasheet 3 abbreviations acronym description acmp analog comparator controller adc analog - to - digital converter ahb a dvanced h igh - p erformance b us apb advanced peripheral bus bod brown - out detection dap debug access port fifo first in, first out fmc flash memory controller gpio general - purpose input/output hclk the clock of a dvanced h igh - p erformance b us hirc 22.1184 mhz i nternal h igh s peed rc o scillator hxt 4~24 mhz e xternal h igh s peed c rystal o scillator icp in circuit programming isp in system programming isr i nterrupt s ervice r outine ldo low dropout regulator lirc 10 khz internal low speed rc oscillator (lirc) lxt 32.768 khz external low speed crystal oscillator nvic nested vectored interrupt controller pclk the clock of advanced peripheral bus pw m pulse width modulation spi serial peripheral interface sps samples per second tmr timer controller uart universal asynchronous receiver/transmitter ucid unique customer id wdt watchdog timer table 4.1 - 1 list of abbreviations
n umicro m ini51 ? de series datasheet may 22, 2014 page 13 of 70 revision 1.01 numicro m ini51 ? de series datasheet 4 parts information li st and pin c onfiguration numicro mini51 ? series selection code 4.1 cpu core arm cortex m0 package type z: qfn 33 (5x5) l: lqfp 48 (7x7 ) f: tssop20 flash rom 51: 4 kb flash rom 52: 8 kb flash rom temperature e: - 40 ~ +105 version d: version mini 5x - x x e 54: 16 kb flash rom t: qfn 33 (4x4) h: version c: - 40 ~ +125 figure 4.1 - 1 numicro mini51 ? series selection code
n umicro m ini51 ? de series datasheet may 22, 2014 page 14 of 70 revision 1.01 numicro m ini51 ? de series datasheet numicro m ini 51 ? series product selection guide 4.2 part no. aprom ram data flash isp loader rom i/o timer connectivity comp. pwm adc isp icp iap irc 22.1184 mhz package uart spi i 2 c mini51fde 4 kb 2 kb configurable 2 kb up to 17 2x 32- bit 1 1 1 - 3 4x10 - bit v v tssop20 mini51l de 4 kb 2 kb configurable 2 kb up to 3 0 2 x 32- bit 1 1 1 2 6 8x1 0 - bit v v lqfp48 mini51z de 4 kb 2 kb configurable 2 kb up to 29 2 x 32- bit 1 1 1 2 6 8x1 0 - bit v v qfn33 (5x5) mini51 tde 4 kb 2 kb configurable 2 kb up to 29 2 x 32- bit 1 1 1 2 6 8x1 0 - bit v v qfn33 (4x4) mini52fde 8 kb 2 kb configurable 2 kb up to 17 2x 32- bit 1 1 1 - 3 4x10 - bit v v tssop20 mini52l de 8 kb 2 kb configurable 2 kb up to 30 2 x 32- bit 1 1 1 2 6 8x1 0 - bit v v lqfp 48 mini52z de 8 kb 2 kb configurable 2 kb up to 2 9 2 x 32- bit 1 1 1 2 6 8x1 0 - bit v v qfn33 (5x5) mini52 tde 8 kb 2 kb configurable 2 kb up to 2 9 2 x 32- bit 1 1 1 2 6 8x1 0 - bit v v qfn33 (4x4) mini54fde 16 kb 2 kb configurable 2 kb up to 17 2x 32- bit 1 1 1 - 3 4x10 - bit v v tssop20 mini54l de 16 kb 2 kb configurable 2 kb up to 3 0 2 x 32- bit 1 1 1 2 6 8x1 0 - bit v v lqfp48 mini54z de 16 kb 2 kb configurable 2 kb up to 29 2 x 32- bit 1 1 1 2 6 8x1 0 - bit v v qfn33 (5x5) mini54 tde 16 kb 2 kb configurable 2 kb up to 29 2 x 32- bit 1 1 1 2 6 8x1 0 - bit v v qfn33 (4x4) *mini54fhc 16 kb 2 kb configurable 2 kb up to 17 2x 32- bit 1 1 1 - 6 3x10 - bit v v tssop20 table 4.2 - 1 numicro mini51 ? series product selection guide * mini54fhc is a special part number, not pin to pin compatible to others mini51series part number.
n umicro m ini51 ? de series datasheet may 22, 2014 page 15 of 70 revision 1.01 numicro m ini51 ? de series datasheet p in configuration 4.3 4.3.1 lqfp 48 -pin 2 44 1 4 3 6 5 8 7 10 9 11 48 42 41 40 39 38 37 32 33 30 31 28 29 26 27 25 13 14 15 16 18 19 20 21 22 12 17 23 24 34 35 36 46 47 43 45 mini51 lqfp 48-pin nc acmp0_p, ain5, p1.5 /reset av ss p5.4 acmp1_p, ain7, p3.1 acmp1_p, sda, t0, p3.4 acmp1_p, scl, t1, p3.5 acmp1_p, t0ex, stadc, int0, p3.2 p5.1,xtal2 p5.0,xtal1 v ss p5.2, int1 ldo_cap p2.2, pwm0 p2.3, pwm1 p2.4, pwm2 p5.5 p3.6, cko,t1ex,acmp0_o p0.7, spiclk p4.6, ice_clk p0.6, miso p0.5, mosi p0.4, spiss,pwm5 p2.5, pwm3 p2.6, pwm4, acmp1_o nc p4.7, ice_dat nc acmp0_p, tx ,ain3,p1.3 acmp0_p, rx ,ain2, p1.2 acmp0_n,ain4,p1.4 acmp0_p, ain1,p1.0 ain0,p5.3 nc av dd nc tx, ctsn, p0.0 spiss, rx, rtsn, p0.1 v dd nc acmp1_n, ain6, p3.0 nc nc nc nc nc nc figure 4.3 - 1 numicro m ini 51 ? series lqfp 48 - pin diagram
n umicro m ini51 ? de series datasheet may 22, 2014 page 16 of 70 revision 1.01 numicro m ini51 ? de series datasheet 4.3.2 qfn 3 3 -pin acmp0_p,ain5, p1.5 p5.4 acmp1_n,ain6, p3.0 acmp1_p,ain7, p3.1 acmp1_p, sda, t0, p3.4 acmp1_p, scl, t1, p3.5 p5.1,xtal2 p5.0,xtal1 v ss p5.2,int1 p2.2, pwm0 p2.3, pwm1 p2.4, pwm2 p3.6, cko,t1ex,acmp0_ o p0.7, spiclk p4.6, ice_clk p0.6, miso p0.5, mosi p0.4, spiss ,pwm5 p2.5, pwm3 p2.6, pwm4,acmp1_o p4.7, ice_dat acmp0_p,tx, ain 3, p1.3 acmp0_p,rx, ain2, p1 .2 acmp0_n,ain4, p1.4 acmp0_p,ain1, p1.0 tx,ctsn, p0.0 v dd spiss,rx,rtsn, p0.1 ain0,p5.3 33 v ss 32 1 24 mini51 qfn 33-pin 31 30 29 28 27 26 25 23 22 21 20 19 18 17 10 9 11 12 13 14 15 16 2 3 4 5 6 7 8 top transparent view acmp1_p, t0ex,stadc,int0, p3.2 /reset figure 4.3 - 2 numicro m ini 51 ? series qfn 33 - pin diagram
n umicro m ini51 ? de series datasheet may 22, 2014 page 17 of 70 revision 1.01 numicro m ini51 ? de series datasheet 4.3.3 tssop 20 -pin 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 rx,ain2,p1.2 tx,ain3,p1.3 ain4,p1.4 ain5,p1.5 /reset int0,toex,stadc,p3.2 t0,sda,p3.4 t1,scl,p3.5 xtal2,p5.1 xtal1,p5.0 v dd p0.4,spiss,pwm5 p0.5,mosi p0.6,miso p0.7,spiclk p4.7,ice_dat p4.6,ice_clk p2.5,pwm3 p2.4,pwm2 v ss mini51 ssop 20-pin figure 4.3 - 3 numicro m ini 51 ? series tssop 20- pin diagram 4.3.4 mini54fhc (tssop20 -pin) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 v dd rx,ain2,p1.2 tx,ain3,p1.3 ain4,p1.4 /reset int0,toex,stadc,p3.2 t0,sda,p3.4 t1,scl,p3.5 vss pwm0,p2.2 p0.4,spiss,pwm5 p0.5,mosi p0.6,miso p0.7,spiclk p4.7,ice_dat p4.6,ice_clk p2.6,pwm4 p2.5,pwm3 p2.4,pwm2 p2.3,pwm1 mini54fhc ssop 20-pin figure 4.3 - 4 numicro m ini 51 ? series tssop 20- pin diagram
n umicro m ini51 ? de series datasheet may 22, 2014 page 18 of 70 revision 1.01 numicro m ini51 ? de series datasheet pin description 4.4 pin number pin name pin type description lqfp 48- pin qfn 33- pin tssop 20- pin mini54fhct ssop20 - pin 1 --- --- --- nc --- not connected 2 1 4 --- p 1 . 5 i/o general purpose digital i/o pin ain5 ai adc analog input pin acmp0_p ai analog comparator positive input pin 3 2 5 5 /reset i(st ) th e schmitt trigger input pin for hardware device reset. a ? low ? on this pin for 768 clock counter of internal rc 22.1184 mhz while the system clock is running will reset the device. /reset pin has an internal pull - up resistor allowing power - on reset by simpl y connecting an external capacitor to gnd. 4 3 --- --- p 3 . 0 i/o general purpose digital i/o pin ain6 ai adc analog input pin acmp1_n ai analog comparator negative input pin 5 --- --- --- av ss ap ground pin for analog circuit 6 4 --- --- p 5 . 4 i/o general purpose digital i/o pin 7 5 --- --- p3.1 i/o general purpose digital i/o pin ain7 ai adc analog input pin acmp1_p ai analog comparator positive input pin 8 6 6 6 p3.2 i/o general purpose digital i/o pin int0 i external interrupt 0 input pin stadc i adc external trigger input pin t0ex i timer 0 external capture/reset trigger input pin acmp1_p ai analog comparator positive input pin 9 7 7 7 p 3 . 4 i/o general purpose digital i/o pin t0 i/o timer 0 external event counter input pin sda i/o i 2 c data i/o pin acmp1_p ai analog comparator positive input pin 10 8 8 8 p 3 . 5 i/o general purpose digital i/o pin t1 i/o timer 1 external event counter input pin scl i/o i 2 c clock i/o pin acmp1_p ai analog comparator positive input pin 11 --- --- --- nc --- not connected. 12 --- --- --- nc --- not connected. 13 --- -- -- nc --- not connected.
n umicro m ini51 ? de series datasheet may 22, 2014 page 19 of 70 revision 1.01 numicro m ini51 ? de series datasheet pin number pin name pin type description lqfp 48- pin qfn 33- pin tssop 20- pin mini54fhct ssop20 - pin 14 9 --- --- p 3 . 6 i/o general purpose digital i/o pin . acmp0_o o analog comparator output pin. cko o frequency divider output pin. t1ex i timer 1 external capture/reset trigger input pin. 15 10 9 --- p 5 .1 i/o general purpose digital i/o pin . xtal2 o the output pin from the internal inverting amplifier. it emits the inverted signal of xtal1. 16 11 10 --- p 5 . 0 i/o general purpose digital i/o pin . xtal1 i the input pin to the internal inverting amplifier. the system clock could be from external crystal or resonator. 17 12 11 9 v ss p ground pin for digital circuit. 33 18 --- --- --- ldo_cap p ldo output pin . 19 --- --- --- p 5 . 5 i/o general purpose digital i/o pin . user program must enable pull - up resistor in the qfn - 33 package. 20 13 --- --- p 5 . 2 i/o general purpose digital i/o pin . int1 i external interrupt 1 input pin. 21 --- --- --- nc --- not connected. 22 14 --- 10 p 2 . 2 i/o general purpose digital i/o pin . pw m0 o pwm0 output of pwm unit. 23 15 --- 11 p2.3 i/o general purpose digital i/o pin . pw m1 o pwm1 output of pwm unit. 24 16 12 12 p2.4 i/o general purpose input/output digital pin . pw m2 o pwm2 output of pwm unit. 25 17 13 13 p2.5 i/o general purpose digital i/o pin . pw m3 o pwm3 output of pwm unit. 26 18 --- 14 p 2 . 6 i/o general purpose digital i/o pin . pw m4 o pwm4 output of pwm unit. acmp1_o o analog comparator output pin. 27 --- --- --- nc --- not connected. 28 --- --- --- nc --- not connected. 29 19 14 15 p4.6 i/o general purpose digital i/o pin .
n umicro m ini51 ? de series datasheet may 22, 2014 page 20 of 70 revision 1.01 numicro m ini51 ? de series datasheet pin number pin name pin type description lqfp 48- pin qfn 33- pin tssop 20- pin mini54fhct ssop20 - pin ice_clk i serial wired debugger clock pin. 30 20 15 16 p4.7 i/o general purpose digital i/o pin . ice_dat i/o serial wired debugger data pin. 31 --- --- --- nc --- not connected. 32 21 16 17 p0 .7 i/o general purpose digital i/o pin . spiclk i/o spi serial clock pin. 33 22 17 18 p 0 . 6 i/o general purpose digital i/o pin . miso i/o spi miso (master in/slave out) pin. 34 23 18 19 p 0 . 5 i/o general purpose digital i/o pin . mosi o spi mosi (master out/slave in) pin. 35 24 19 20 p 0 . 4 i/o general purpose digital i/o pin . spiss i/o spi slave select pin. pw m5 o pwm5 output of pwm unit. 36 --- --- --- nc --- not connected. 37 25 --- --- p 0 . 1 i/o general purpose digital i/o pin . rtsn o uart rts pin. rx i uart data receiver input pin. spiss i/o spi slave select pin. 38 26 --- --- p 0 . 0 i/o general purpose digital i/o pin . ctsn i uart cts pin. tx o uart transmitter output pin. 39 --- --- --- nc --- not connected. 40 --- --- --- nc --- not connected. 41 27 --- --- p 5 . 3 i/o general purpose digital i/o pin . ain0 ai adc analog input pin. 42 28 20 1 v dd p power supply for digital circuit. 43 av dd p power supply for analog circuit. 44 29 --- --- p 1 . 0 i/o general purpose digital i/o pin . ain1 ai adc analog input pin. acmp0_p ai analog comparator positive input pin. 45 30 1 2 p 1 . 2 i/o general purpose digital i/o pin . ain2 ai adc analog input pin.
n umicro m ini51 ? de series datasheet may 22, 2014 page 21 of 70 revision 1.01 numicro m ini51 ? de series datasheet pin number pin name pin type description lqfp 48- pin qfn 33- pin tssop 20- pin mini54fhct ssop20 - pin rx i uart data receiver input pin. acmp0_p ai analog comparator positive input pin. 46 31 2 3 p 1 . 3 i/o general purpose digital i/o pin . ain3 ai adc analog input pin. tx o uart transmitter output pin. acmp0_p ai analog comparator positive input pin. 47 32 3 4 p 1 . 4 i/o general purpose digital i/o pin . ain4 i/o pw m 5: pwm output /capture input. acmp0_n ai analog comparator negative input pin. 48 --- -- -- nc --- not connected. [1] i/o type description. i: input, o: output, i/o: quasi bi - direction, d: open - drain, p: power pin, st: schmitt trigger , a: analog inpu t.
n umicro m ini51 ? de series datasheet may 22, 2014 page 22 of 70 revision 1.01 numicro m ini51 ? de series datasheet 5 block diagram numicro m ini 51? block diagram 5.1 figure 5.1 - 1 numicro m ini 51 ? series block diagram
n umicro m ini51 ? de series datasheet may 22, 2014 page 23 of 70 revision 1.01 numicro m ini51 ? de series datasheet 6 functional descripti on memory organization 6.1 6.1.1 overview the numicro m ini 51 ? series provides 4g - byte address ing space. the addressing space assigned to each on - chip controllers is shown the following table . the detailed register definition, addressing space, and programming details will be described in the following sections for each on - c hip peripheral . the numicro m ini 51 ? series only supports little - endian data format. 6.1.2 system memory map the memory locations assigned to each on - chip controllers are shown in the following table . address ing space token module s flash and sram memory space 0x0000_0000 ? 0x000 0 _ 3 fff flash_ba f lash memory space (1 6 kb) 0x2000_0000 ? 0x2000_ 07 ff sram_ba sram memory space ( 2 kb) ahb module s space (0x5000_0000 ? 0x501f_ffff) 0x5000_0000 ? 0x5000_01ff gcr_ba system global control registers 0x5000_0200 ? 0x5000_02ff clk_ba clock control registers 0x5000_0300 ? 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 ? 0x5000_7fff gp_ba gpio (p0~p5) control registers 0x5000_c000 ? 0x5000_ffff fmc_ba flash memory control registers apb module s space (0x4000_0000 ? 0x40 1 f_ffff) 0x4000_4000 ? 0x4000_7fff wdt_ba watchdog timer control registers 0x4001_0000 ? 0x4001_3fff tmr_ba timer0 /timer1 control registers 0x4002_0000 ? 0x4002_3fff i2c_ba i 2 c interface control registers 0x4003_0000 ? 0x4003_3fff spi_ba spi with master/slave function control registers 0x4004_0000 ? 0x4004_3fff pw m_ba pwm control registers 0x4005_0000 ? 0x4005_3fff uart_ba uart control registers 0x400d_0000 ? 0x400d_3fff a cmp_ba analog comparator control registers 0x400e_0000 ? 0x400e_ 3 fff adc_ba analog - digital - converter (adc) control registers system control space (0x e000 _ e 000 ? 0x e000 _ e fff) 0x e000 _ e 0 1 0 ? 0x e000 _ e0f f scs_ba system timer control registers 0x e000 _ e10 0 ? 0x e000 _ ecf f scs_ba nested vectored interrupt control registers 0x e000 _ ed0 0 ? 0x e000 _ ed8 f scb_ba system control block registers table 6.1 - 1 address space assignments for on - chip modules
n umicro m ini51 ? de series datasheet may 22, 2014 page 24 of 70 revision 1.01 numicro m ini51 ? de series datasheet nested vectored interrupt controller (nvic) 6.2 6.2.1 overview the cortex? - m0 cpu provides an interrupt controller as an integral part of the exception mode, named as ?nested vectored interrupt controller (nvic)? , which is closely coupled to the processor core and pro vides following features . 6.2.2 feature s ? nested and vectored interrupt support ? automatic processor state saving and restoration ? dynamic priority chang e ? reduced and deterministic interrupt latency the nvic prioritizes and handles all supported exceptions. all exceptions are handled in ?handler m ode?. this nvic arch itecture supports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will compare the priority of the new interrupt to the current running one?s priority. if the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. when an interrupt is accepted, the starting address of the i nterrupt s ervice r outine (isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the starting address of the correlated isr by software. while the starting address is fetched, nvic will also automatically sav e processor state including the registers ?pc, psr, lr, r0~r3, r12? to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume the normal execution. thus it will take less and deterministic time to process the interrupt request. the nvic supports ?tail chaining? which handles back - to - back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending isr at the end of current isr. the nvic a lso supports ?late arrival? which improves the efficiency of concurrent isrs. when a higher priority interrupt request occurs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penalty. thus it advances the real - time capability. for more detailed information, please refer to the ?arm ? cortex? - m0 technical reference manual? and ?arm ? v6 - m architecture reference manual?.
n umicro m ini51 ? de series datasheet may 22, 2014 page 25 of 70 revision 1.01 numicro m ini51 ? de series datasheet 6.2.3 exception model and sys tem interrupt map the following table lists t he exception model supported by numicro m ini 51 ? series. software can set four levels of priority on some of these exceptions as well as on all interrupts. the highest user - configurable priority is denoted as 0 and the lowest priority is denoted as 3. the default priority of all the user - configurable int errupts is 0. note that the priority 0 is treated as the fourth priority on the system, after three system exceptions ?reset?, ?nmi? and ?hard fault?. exception name vector nu mber priority reset 1 - 3 nmi 2 - 2 hard fault 3 - 1 reserved 4 ~ 10 reserved svcall 11 configurable reserved 12 ~ 13 reserved pendsv 14 configurable systick 15 configurable interrupt (irq0 ~ irq31) 16 ~ 47 configurable table 6.2 - 1 exception model exception nu mber i nterrupt nu mber ( bit i n interrupt registers ) interrupt name source module interrupt d escription power - d own w ake - u p 1 ~ 15 - - - system exceptions - 16 0 bod_out brown - o ut brown - o ut low voltage detected interrupt yes 17 1 wdt_int wdt watch d og timer interrupt yes 18 2 eint 0 gpio external signal interrupt from p3.2 pin yes 19 3 eint 1 gpio external signal interrupt from p5.2 pin yes 20 4 gp 0/1 _int gpio external signal interrupt from gpio group p0~p1 yes 21 5 gp 2/3/4 _int gpio external signal interrupt from gpio group p2~p4 except p3.2 yes 22 6 pwm_int pw m pw m interrupt no 23 7 brake _int pw m pw m interrupt no 24 8 tmr0_int tmr0 timer 0 interrupt yes 25 9 tmr1_int tmr1 timer 1 interrupt yes 26 ~ 27 10 ~ 11 - - - 28 12 uart_int uart uart interrupt yes
n umicro m ini51 ? de series datasheet may 22, 2014 page 26 of 70 revision 1.01 numicro m ini51 ? de series datasheet exception nu mber i nterrupt nu mber ( bit i n interrupt registers ) interrupt name source module interrupt d escription power - d own w ake - u p 29 13 - - - 30 14 spi_ int spi spi interrupt no 31 15 - - - 32 16 gp5 _int gpio external signal interrupt from gpio group p5 except p5.2 yes 33 17 hirc _trim_in t hirc hirc trim interrupt no 34 18 i2c_int i 2 c i 2 c interrupt yes 35 ~ 40 19 ~ 24 - - - 41 25 acmp_int a cmp analog comparator 0 or comparator 1 interrupt yes 42 ~ 43 26 ~ 27 - - - 44 28 pwrwu_int clkc clock controller interrupt for chip wake - up from p o wer - down state yes 45 29 adc_int adc adc interrupt no 46 ~ 47 30 ~ 31 - - - table 6.2 - 2 system interrupt map vector table 6.2.4 vector table when an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (isr) from a vector table in memory. for armv6 - m, the vector table base d address is fixed at 0x00000000. the vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. the vector number on previous page defines the orde r of entries in the vector table associated with the exception handler entry as illustrated in previous section. vector table word offset ( bytes ) description 0 x00 initial stack pointer v alue exception number * 0x04 exception entry pointer using that exception number table 6.2 - 3 vector table format
n umicro m ini51 ? de series datasheet may 22, 2014 page 27 of 70 revision 1.01 numicro m ini51 ? de series datasheet 6.2.5 operation description nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set - enable or interrupt clear - enable register bit - field. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current enabled state of the corresponding interrupts. when an interrupt is disabled, interrupt assertion will cause the interrupt to become pend ing ; however, the interrupt will not be activate d . if an interrupt is active when it is disabled, it remains in its active state until cleared by reset or an exception return. clearing the enable bit prevents new activations of the associated interrupt. nv ic interrupts can be pended/un - pended using a complementary pair of registers to those used to enable/disable the interrupts, named the set - pending register and clear - pending register respectively. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current pended state of the corresponding interrupts. the clear - pending register has no effect on the execution status of an active interrupt. nvic interrupts are prioritized by updating an 8 - bit field within a 32 - b it register (each register supporting four interrupts). the general registers associated with the nvic are all accessible from a block of memory in the system control space and will be described in next section.
n umicro m ini51 ? de series datasheet may 22, 2014 page 28 of 70 revision 1.01 numicro m ini51 ? de series datasheet system manager 6.3 6.3.1 overview s ystem manage ment include s t he following section s: ? system reset ? system power architecture ? system memory map ? system management registers for part number id , chip reset and on - chip controllers reset, and multi - functional pin control ? system timer (systick) ? nested vectored interrupt controller (nvic) ? system control registers 6.3.2 system reset the system reset can be include d by one of the following listed events . for these reset event s flags can be read by rst s rc register. ? power - on reset (por) ? l ow level on the r eset p in (/reset) ? watchdog timer time - o ut reset (wdt) ? brown - o ut detect o r reset (bod) ? cortex? - m0 mcu reset ? cpu reset 6.3.3 system power architecture in this chip , the power distribution is divided into three segments. ? a nalog power from av dd and av ss provides the power for analog components operation . av dd must be equal to v dd to avoid leakage current . ? digital power from v dd and v ss supplies power to the i/o pins and internal regulator which provides a fixed 1.8v power for digital operation . ? build - in a capacitor for internal voltage regulator the output of internal voltage regulator, ldo_cap, require s an external capacitor which should be located close to the corresponding pin. analog power (av dd ) should be the same voltage level as the digital power (v dd ). the following figure shows the power distribution of th e mini51 tm de series .
n umicro m ini51 ? de series datasheet may 22, 2014 page 29 of 70 revision 1.01 numicro m ini51 ? de series datasheet 5v to 1.8v ldo 10-bit sar-adc brown out detector por18 low voltage reset analog comparator flash digital logic 1.8v internal 22.1184 mhz and 10 khz oscillator av dd av ss v dd v ss ldo_cap io cell gpio pins mini51 tm series power distribution figure 6.3 - 1 numicro m ini 51 ? series power architecture diagram
n umicro m ini51 ? de series datasheet may 22, 2014 page 30 of 70 revision 1.01 numicro m ini51 ? de series datasheet 6.3.4 whole system memory m apping table 6.3 - 1 memory m apping t able mini51/52/54 system control 4 gb 0xffff_ffff system control 0xe000_ed00 scs_ba | external interrupt control 0xe000_e100 scs_ba 0xe000_f000 system timer control 0xe000_e010 scs_ba 0xe000_efff 0xe000_e000 0xe000_e00f | 0x6002_0000 0x6001_ffff 0x6000_0000 0x5fff_ffff | 0x5020_0000 ahb peripherals 0x501f_ffff fmc 0x5000_c000 fmc_ba 0x5000_0000 gpio control 0x5000_4000 gp_ba 0x4fff_ffff interrupt multiplexer control 0x5000_0300 int_ba clock control 0x5000_0200 clk_ba system global control 0x5000_0000 gcr_ba 0x4020_0000 0x401f_ffff 1 gb 0x4000_0000 0x3fff_ffff apb peripherals adc control 0x400e_0000 adc_ba acmp control 0x400d_0000 cmp_ba uart control 0x4005_0000 uart_ba 0x2000_0800 pwm control 0x4004_0000 pwm_ba 0x2000_07ff spi control 0x4003_0000 spi_ba 0.5 gb 0x2000_0000 i2c control 0x4002_0000 i2c_ba 0x1fff_ffff timer0/timer1 control 0x4001_0000 tmr_ba wdt control 0x4000_4000 wdt_ba 0x0000_4000 16 kb on-chip flash (mini54) 0x0000_3fff 8 kb on-chip flash (mini52) 0x0000_1fff 0x0000_0fff 0 gb 0x0000_0000 | | | | system control reserved 4 kb on-chip flash (mini51) 2 kb sram reserved reserved reserved reserved apb reserved ahb reserved
n umicro m ini51 ? de series datasheet may 22, 2014 page 31 of 70 revision 1.01 numicro m ini51 ? de series datasheet clock controller 6.4 6.4.1 overview the clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. the clock controller also implements the power control function with the individually clock on/off control, clock source selection and clock divide r. the chip enters power - down mode when cortex? - m0 core executes the wfi instruction only if the pwr_down_en (pwrcon[7]) bit and pd_wait_cpu (pwrcon[8]) bit are both set to 1. after that, chip enters power - down mode and waits for wake - up interrupt source t riggered to exit power - down mode. in power - down mode, the clock controller turns off the 4~24 mhz external high speed crystal (hxt) and 22.1184 mhz internal high speed rc oscillator (hirc) to reduce the overall system power consumption. the following figur es show the clock generator and the overview of the clock source control. the clock generator consists of 3 sources as list ed below: ? 4~24 mhz external high speed crystal oscillator (hxt) or 32 .768 k hz (lxt) external low speed crystal oscillator ? 22 .1184 mh z internal high speed rc oscillator (hirc) ? 10 k hz internal low speed rc oscillator (lirc) xtal2 4~24 mhz hxt or 32.768 khz lxt xtlclk_en (pwrcon[1:0]) xtal1 22.1184 mhz hirc osc22m_en (pwrcon[2]) 10 khz lirc osc10k_en(pwrcon[3]) hxt or lxt hirc lirc legend: hxt = 4~24 mhz external high speed crystal oscillator lxt = 32.768 khz external low speed crystal oscillator hirc = 22.1184 mhz internal high speed rc oscillator lirc = 10 khz internal low speed rc oscillator figure 6.4 - 1 clock g enerator b lock d iagram
n umicro m ini51 ? de series datasheet may 22, 2014 page 32 of 70 revision 1.01 numicro m ini51 ? de series datasheet 6.4.2 system clock and systick clock the system clock has three clock sources which are generated from clock generator block. the clock source switch es depend ing on the register hclk_s (clksel0[2:0]). the block diagram is shown below. 111 011 010 001 reserved reserved 4~24 mhz hxt or 32.768 khz lxt 10 khz lirc hclk_s (clksel0[2:0]) 22.1184 mhz hirc 000 1/(hclk_n+1) hclk_n (clkdiv[3:0]) cpu in power down mode cpu ahb apb cpuclk hclk pclk legend: hxt = 4~24 mhz external high speed crystal oscillator hirc = 22.1184 mhz internal high speed rc oscillator lirc = 10 khz internal low speed rc oscillator figure 6.4 - 2 system clock block diagram the clock source of systick in cortex tm - m0 core can use cpu clock or external clock (syst_csr[2]). i f using external clock, the systick clock (stclk) has 4 clock sources. the clock source switch e s depend ing on the setting of the register stclk_s (clksel0[5:3] ) . the block diagram is shown below . 111 010 hclk 4~24 mhz hxt or 32.768 khz lxt stclk_s (clksel0[5:3]) stclk 22.1184 mhz hirc 001 1/2 1/2 4~24 mhz hxt or 32.768 khz lxt 011 1/2 000 reserved legend: hxt = 4~24 mhz external high speed crystal oscillator hirc = 22.1184 mhz internal high speed rc oscillator lirc = 10 khz internal low speed rc oscillator figure 6.4 - 3 systick c lock control block diagram
n umicro m ini51 ? de series datasheet may 22, 2014 page 33 of 70 revision 1.01 numicro m ini51 ? de series datasheet 6.4.3 isp clock source select ion the clock source of isp is from ahb clock (hclk). please refer to the register ahbclk. isp _ en ( ahbclk [2 ]) hclk isp ( in system programmer ) figure 6.4 - 4 ahb clock source for hclk 6.4.4 module clock source select ion the peripheral clock ha s different clock source switch setting s depend ing on different peripheral s . please refer to the clksel1 and apbclk register description in section error! reference source not found. . wdt_en (apbclk[0 ]) pclk watch dog timer timer1 timer0 tmr0_en (apbclk[ 2]) tmr1_en (apbclk[3]) fdiv_en (apbclk[6 ]) i2c_en (apbclk[8]) spi_en ( apbclk[12]) uart_en (apbclk[16]) pwm01_en (apbclk[20]) pwm23_en (apbclk[21]) pwm45_en (apbclk[22]) cmp_en (apbclk[30]) adc_en (apbclk[28]) frequency divider i2c spi uart pwm01 pwm23 pwm45 acmp adc figure 6.4 - 5 peripherals clock source select ion for pclk
n umicro m ini51 ? de series datasheet may 22, 2014 page 34 of 70 revision 1.01 numicro m ini51 ? de series datasheet ext . clk ( hxt o r lxt ) hirc lirc pclk wdt yes no yes yes timer0 yes yes yes yes timer1 yes yes yes yes i 2 c no no no yes spi no no no yes uart yes yes no no pwm no no no yes adc yes yes no yes acmp no no no yes table 6.4 - 1 peripheral clock source select ion t able 6.4.5 power -d own mode clock when chip enter s power - d own m ode , system clocks, some clock sources , and some peripheral clock s will be disable d . some clock sources and peripheral clock s are still active in p ower - down mode. the c locks still kep t active are list ed below: ? cl ock generator ? 10 k hz internal low speed oscillator (lirc) clock ? 32.768 k hz e xternal low speed crystal oscillator (lxt) clock (if pd_32k = 1 and xtlclk_en[1:0] = 10) ? peripheral s clock (when 10 khz low speed oscillator is adopted as clock source) ? watchdog clock ? timer 0/1 clock 6.4.6 frequency divider output this device is equipped with a power - of - 2 frequency divider which is composed of 16 chained divide - by - 2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is reflec ted to the cko pin . therefore there are 16 options of power - of - 2 divided clocks with the frequency from f in /2 1 to f in /2 1 6 where f in is input clock frequency to the clock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequen cy, f out is the clock divider output frequency and n is the 4 - bit value in fsel ( frqdiv[3:0] ) . when writing 1 to divider_en ( frqdiv[4] ) , the chained counter starts to count. when writing 0 to divider_en ( frqdiv[4] ) , the chained counter continuously runs til l divided clock reaches low state and stay in low state. if divider1(frqdiv[5]) is set to 1, the frequency divider clock (frqdiv_clk) will bypass power - of - 2 frequency divider. the frequency divider clock will be output to cko pin directly.
n umicro m ini51 ? de series datasheet may 22, 2014 page 35 of 70 revision 1.01 numicro m ini51 ? de series datasheet 11 10 01 00 hclk reserved 4~24 mhz hxt or 32.768 khz lxt 22.1184 mhz hirc frqdiv_s (clksel2[3:2]) fdiv_en (apbclk[6]) frqdiv_clk legend: hxt = 4~24 mhz external high speed crystal oscillator lxt = 32.768 khz external low speed crystal oscillator hirc = 22.1184 mhz internal high speed rc oscillator figure 6.4 - 6 clock source of frequency divider 000 0 000 1 111 0 111 1 : : 16 to 1 mux 1/2 1/2 2 1/2 3 1/2 15 1/2 16 ?... fsel (frqdiv[3:0]) cko 16 chained divide-by-2 counter divider_en (frqdiv[4]) enable divide-by-2 counter 0 1 divider1 (frqdiv[5]) frqdiv_clk figure 6.4 - 7 block diagram of frequency divider
n umicro m ini51 ? de series datasheet may 22, 2014 page 36 of 70 revision 1.01 numicro m ini51 ? de series datasheet analog comparator ( a cmp) 6.5 6.5.1 overview the numicro m ini 51 ? series contains two comparators which can be used in a number of different configurations. the comparator output is logic 1 when positive input greater than negative input , otherwise the output is 0 . each comparator can be configured to generate interrupt when the comparator output value changes. 6.5.2 features ? analog input voltage range: 0 ~ av dd ? s upport s hysteresis function ? o ptional internal reference voltage source for each comparator negative input
n umicro m ini51 ? de series datasheet may 22, 2014 page 37 of 70 revision 1.01 numicro m ini51 ? de series datasheet analog - to - digital converter (adc) 6.6 6.6.1 overview the numicro m ini 51 ? series contain s one 10- bit successive approximation analog - to - digital converters (sar a/d converter) with eight input channels. the a/d converters can be started by software , external pin ( stadc/ p3.2 ) or pwm trigger . 6.6.2 features ? analog input voltage range: 0 ~ analog supply voltage from av dd ? 10- bit resolution and 8 - bit accuracy is guaranteed ? up to eight single - end analog input channels ? 300 ksps (av dd 4.5v - 5.5v) and 200 ksps (av dd 2.5v - 5.5v ) conversion rate ? an a/d conversion is performed one time on a specified channel ? an a/d conversion can be started by : ? software write 1 to adst bit ? external pin stadc ? pwm trigger with optional start delay period ? each c onversion result is held in data register with valid and overrun indicators ? conversion result s can be compared with specif ied value and user can select whether to generate an interrupt when conversion result matches the compare register setting ? channel 7 supports 2 i nput sources: e xternal analog voltage and internal fixed band - gap voltage
n umicro m ini51 ? de series datasheet may 22, 2014 page 38 of 70 revision 1.01 numicro m ini51 ? de series datasheet f lash memory controller (fmc) 6.7 6.7.1 overview the n u m icro m ini 51 tm series is equip ped with 4k/ 8 k/16k bytes on chip embedded f lash memory for application program (aprom) that can be updated through isp procedure. in - system - programming (isp) and in - application - programming (iap) enable user to update program memory when chip is soldered on pcb. after chip power on cortex tm - m0 cpu fetches code from aprom or ldrom decided by boot s elect (cbs) in c onfig 0. by the way, the n u m icro m ini 51 tm series also provide s d ata flash region that is shared with aprom and its start address is configurable and defined by user in c onfig 1. 6.7.2 features ? run ning up to 24 mhz with zero wait state for disconti nuous address read access ? 4/ 8/16 kbytes application program memory (aprom) ? 2 k bytes in system programming (isp) loader program memory (ldrom) ? programmable data flash start address ? all embedded flash memory supports 512 bytes page erase ? in system program (isp) /in application program (iap) to update on chip flash memory
n umicro m ini51 ? de series datasheet may 22, 2014 page 39 of 70 revision 1.01 numicro m ini51 ? de series datasheet general purpose i/o (gpio) 6.8 6.8.1 overview the n u m icro m ini 51 tm series have up to 30 general purpose i/o pins to be shared with other function pins depending on the chip configuration . the se 30 p ins are arranged in 6 ports named as p0, p1, p2, p3 , p4 and p 5 . each of the 30 pins is independent and has the corresponding register bits to control the pin mode function and data . the i/o type of each pin can be configured by software individually as i np ut, push - pull output, o pen - drain output , or q uasi - bidirectional mode. for quasi - bidirection al mode, e ach i/o pin is equip ped with a very weak individual pull - up resistor about 110 k ? ~ 300 k ? for v dd is from 5.0 v to 2.5 v. 6.8.2 features ? four i/o modes: ? input - only with high impendence ? push - p ull output ? open - d rain output ? quasi - bidirectional ? ttl/schmitt trigger input mode selected by px_mfp[23:16] ? i/o pin configured as interrupt source with edge/level setting ? i/o pin internal pull - up resistor enabled only in quasi - b i directional i/o mode ? enabl ing the pin interrupt function will also enable the pin wake - up function ? high driver and high sink i / o mode support ? configurable default i/o mode of all pins after reset by cioini ( c onfig0 [10] ) setting ? cioini = 0 , all gpio pins in quasi - bidirectional mode after chip reset ? cioini = 1 , all gpio pins in input tri - state mode after chip reset (default)
n umicro m ini51 ? de series datasheet may 22, 2014 page 40 of 70 revision 1.01 numicro m ini51 ? de series datasheet i 2 c serial interface controller ( i 2 c ) 6.9 6.9.1 overview i 2 c is a two - wire, bi - directional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. the i 2 c also suppor ts power - down wake up function. 6.9.2 features the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus include : ? master/slave mode ? bi - directional data transfer between masters and slaves ? multi - master bus ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allow ing devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? built - in 14 - bit time - out counter that request s the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows ? external pull - up needed for high er output pull - up speed ? program mable clocks allow ing for versatile rate control ? supports 7 - bit addressing mode ? s upport s multiple address recognition ( f our slave address registers with mask option) ? s upport s power - down wake - up function ? support fifo function
n umicro m ini51 ? de series datasheet may 22, 2014 page 41 of 70 revision 1.01 numicro m ini51 ? de series datasheet enhanced pwm generator 6.10 6.10.1 overview the numicro m ini 51 ? series has buil t one pwm unit which is specially designed for motor driving control applications. the pwm unit supports six pwm g enerators which can be configured as six independent pwm outputs, pwm0~pwm 5 , or as three complementary pwm pairs, (pwm0, pwm1), (pwm2, pwm3) and (pwm4, pwm5) with three programmable dead - zone generators. every complementary pwm pairs share one 8 - bit prescaler . there are six c lock divider s providing five divided frequencies (1, 1/2, 1/4, 1/8, 1/16) for each channel . each pwm output has independent 16- bit counter for pwm period control, and 16- bit comparators for pwm duty control . the six pwm g enerators provide twelve independent pwm interrupt flags which are set by hardware when the correspondi ng pwm period counter comparison matched period and duty . each pwm interrupt source with its corresponding enable bit can request pwm interrupt. the pwm g enerators can be configured as o ne- shot mode to produce only one pwm cycle signal or a uto - reload mode to output pwm waveform continuously. to prevent pwm driving output pin with unsteady waveform, the 16 - bit period down counter and 16- bit comparator are implemented with double buffer. when user writes data to counter/comparator buffer registers, the update d value will be loaded into the 16 - bit down counter/ comparator at the end of current period . the double buffering feature avoids glitch at pwm outputs. b esides pwm, m otor controlling also need timer, acmp and adc to work together. in order to control motor more precisely, we provide some registers that not only configure pwm but also t imer , adc and acmp, by doing so, it can save more cpu time and control motor with ease especially in bld c . 6.10.2 features the pwm unit supports the following features: ? indepen d ent 1 6 - bit pwm duty control units with maximum six port pins: ? six independent pwm outputs ? pwm0, pwm1, pwm2, pwm3, pwm4, and pwm5 ? three complementary pwm pairs, with each pin in a pair mutually complement to each other and capable of programmable dead - zone insertion ? (pwm0 , pwm1 ), (pwm2 , pwm3 ) and (pwm4 , pw m5) ? three synchronous pwm pairs, with each pin in a pair in - phase ? (pwm0, pwm1), (pwm2, pwm3) and (pwm4, pwm5) ? group control bit ? pwm2 and pwm4 are synchronized with pwm0 , pwm 3 and pwm 5 are sy nchronized with pwm 1 ? one - shot (only support edge alignment mode) or auto - reload mode pwm ? up to 16 - bit resolutio n ? support s edge - aligned and center - aligned mode ? programmable dead - zone insertion between complementary paired p wms ? each pin of pwm0 to pwm5 has i ndependent polarity setting control ? hardware fault brake protection s
n umicro m ini51 ? de series datasheet may 22, 2014 page 42 of 70 revision 1.01 numicro m ini51 ? de series datasheet ? two interrupt source types: ? s ynchronously requested at pwm frequency when down counter comparison matched (edge - and center - aligned mode) or underflow (edge - aligned mode) ? r equested when external fault brake asserted ? bkp0: e int0 or cpo1 ? bkp1: e int1 or cpo0 ? the pwm signals before polarity control stage are defined in the view of positive logic. the pwm ports is active high or active low are controlled by polarity control register. ? support s independently rising cmr matching (in c enter - aligned mode), cnr matching (in c enter - aligned mode), falling cmr matching, period matching to trigger adc conversion ? t imer comparing matching event trigger pwm to do phase change in bldc application ? support s ac mp output event trigger pwm to force pwm output at most one period low, this feature is usually for step motor control ? p rovide s interrupt accumulation function
n umicro m ini51 ? de series datasheet may 22, 2014 page 43 of 70 revision 1.01 numicro m ini51 ? de series datasheet serial peripheral interface (spi) 6.11 6.11.1 overview the serial peripheral interface (spi) applies to synchronous serial data communication and allows full duplex transfer . devices communicate in m aster/ s lave mode with 4 - wire bi - direction interface. the spi controller performing a serial - to - parallel conversi on on data received from a peripheral device, and a parallel - to - serial conversion on data transmitted to a peripheral device. spi controller can be configured as a master or a slave device . 6.11.2 features ? support s m aster or s lave mode operation ? configurable tra nsfer bit length ? provides four 32 - bit fifo buffer s ? support s msb first or lsb first transfer ? support s byte reorder function ? supports byte or word suspend mod e ? supports slave 3 - w ire mod e
n umicro m ini51 ? de series datasheet may 22, 2014 page 44 of 70 revision 1.01 numicro m ini51 ? de series datasheet timer controller (tmr) 6.12 6.12.1 overview the timer controller includes two 32- bit timers, timer0 ~ timer 1 , allowing user to easily implement a timer control for applications. the timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval mea surement by external capture pins. 6.12.2 features ? two sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit pre - scale counter ? independent clock source for each channel (tmr0_clk, tmr1_clk) ? p rovides four timer counting modes: one - shot, periodic, toggle and continuous counting ? time - out period = ( p eriod of timer clock input) * (8 - bit pre - scale counter + 1) * (24 - bit tcmp) ? maximum counting cycle time = (1 / t mhz) * (2 8 ) * (2 24 ) ; t is the period of timer clock ? 24- bit up counter value is readable through tdr (ti mer data register) ? support s event counting function to count the event from external pin (t0, t1) ? 24- bit capture value is readable through tcap (timer capture data register) ? suppor ts external capture pin (t0ex, t1 ex) for interval measurement ? suppor ts internal signal (cpo0, cpo1 ) for interval measurement ? suppor ts external capture pin (t0ex , t 1 ex) to reset 24 - bit up counter ? supports c hip wake - up from idle/power - down mode if a timer interrupt signal is generated
n umicro m ini51 ? de series datasheet may 22, 2014 page 45 of 70 revision 1.01 numicro m ini51 ? de series datasheet uart controller (uart) 6.13 6.13.1 overview the numicro mini51 ? series provides one channel of universal asynchronous receiver/transmitters (uart). uart controller perform s normal speed uart, and support s flow control function. the uart controller performs a serial - to - parallel conversion on data received from the peripheral, and a parallel - to - serial conversion on data transmitted from the cpu. the uart controller also supports irda sir function, and rs - 485 function mode . 6.13.2 fea tures ? full duplex, asyn chronous communications ? separate s 16- byte receive and transmitted fifo for data payloads ? support s hardware auto flow contro l, f low control function (cts, rts) and programmable rts flow control trigger level ? programmable receiver buffer trigger level ? support s programmable baud - rate generator for each channel individually ? support s cts wake - up function ? support s 8 - bit receiver buffer time - out detection function ? programmable transmitting data delay time between the last stop and the next start bit by setti ng dly( ua_tor[ 15:8 ] ) register ? support s break error, frame error, parity error and receive/transmit buffer overflow detect ion function ? fully programmable serial - interface characteristics ? programmable number of data bit, 5 - , 6 - , 7 - , 8 - bit character ? programmable parity bit, even, odd, no parity or stick parity bit ? programmable stop bit, 1, 1.5, or 2 stop bit ? support s irda sir function mode ? support s 3/16 - bit duration for normal mode ? support s rs - 485 function mode ? support s rs - 485 9- bit mode ? support s hardware or software enable to program rts pin to control rs - 485 trans mission direction directly
n umicro m ini51 ? de series datasheet may 22, 2014 page 46 of 70 revision 1.01 numicro m ini51 ? de series datasheet watchdog timer (wdt) 6.14 6.14.1 overview the purpose of watchdog timer is to perform a system reset when system runs into an unknown state. this prevents system from h anging for an infinite period of time. besides, this watchdog timer supports the function to wake - up system from idle/power - down mode. 6.14.2 features ? 18- bit free running up counter for watchdog timer time - out interval ? selectable time - out interval (2 4 ~ 2 18 ) wdt_ clk cycle and the time - out interval period is 104 ms ~ 26.3168 s if wdt_clk = 10 khz ? system kept in reset state for a period of (1 / wdt_clk) * 63 ? supports watchdog t imer time - out wake - up function only if wdt clock source is selected as 10 khz
n umicro m ini51 ? de series datasheet may 22, 2014 page 47 of 70 revision 1.01 numicro m ini51 ? de series datasheet 7 arm ? cortex? - m0 core overview 7.1 t he cortex? - m0 processor is a configurable, multistage, 32 - bit risc processor which has an amba ahb - lite interface and includes an nvic component. it also has optional hardware debug functionality. the processor can execute thumb code and is compatible with other cortex tm - m profile processor s . the profile supports two modes - thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entered on reset and can be entered as a result of an exception return. the following figure shows the functional controller of the processor. cortex -m0 processor core nested vectored interrupt controller ( nvic) breakpoint and watchpoint unit debugger interface bus matrix debug access port ( dap ) debug cortex -m0 processor cortex -m0 components wakeup interrupt controller ( wic) interrupts serial wire or jtag debug port ahb - lite interface figure 7.1 - 1 functional block diagram feature s 7.2 ? a low gate count processor ? armv6 - m thumb ? instruction set ? thumb - 2 technology ? armv6 - m compliant 24- bit systick timer ? a 32 - bit hardware multiplier ? system interface s upport ed with little - endian data accesses ? ability to have d eter mini stic, fixed - latency, interrupt handling ? load/store - multiples and multicycle - multiplies that can be abandoned and restarted to facilitate rapid interrupt handling ? c application binary interface compliant exception model : this is the armv6 - m, c application binary interface (c - abi) compliant exception model that enables the use of pure c functions as interrupt handlers ? low power idle m ode entry using the wait for interrupt (wfi), wait for even t (wfe) instructions, or return from interrupt sleep - on - exit feature ? nvic
n umicro m ini51 ? de series datasheet may 22, 2014 page 48 of 70 revision 1.01 numicro m ini51 ? de series datasheet ? 32 external interrupt inputs, each with four levels of priority ? dedicated n on - m askable interrupt (nmi) input ? support s for both level - sensitive and pulse - sensitive interrupt lines ? supports wake - up interrupt controller (wic) and, providing u ltra - low p ower idle m ode ? debug support ? four hardware breakpoints ? two watch points ? program counter sampling register (pcs r) for non - intrusive code profiling ? single step and vector catch capabilities ? bus interfaces ? single 32 - bit amba - 3 ahb - lite system interface that provides simple integration to all system peripherals and memory ? single 32 - bit slave port that supports the dap ( debug access port ) system timer (systick) 7.3 the cortex ?- m0 includes an integrated system timer, systick , which provides a simple, 24 - bit clear - on - write, decrementing, wrap - on - zero counter with a flexible control mechanism. the counter can be used as a real time operating system (rtos) tick timer or as a simple counter. when system timer is enabled, it will count d own from the value in the systick current value register (syst_cvr) to zero, and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock edge, and then decrement on subsequent clocks. when the counter transitions to zer o, the countflag status bit is set. the countflag bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to zero before enabling the feature. this ensures the timer to count from the syst_rvr value ra ther than an arbitrary value when it is enabled. if the syst_rvr is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to the ?arm ? cortex? - m0 technical reference manual? and ?arm ? v6 - m architecture reference manual?.
n umicro m ini51 ? de series datasheet may 22, 2014 page 49 of 70 revision 1.01 numicro m ini51 ? de series datasheet 8 application circui t av ss av dd avcc dvcc v ss v dd 4~24 mhz crystal 0.1uf fb fb 20p 20p dvcc 10uf/25v 10k power crystal reset circuit /reset xtal2 ldo_cap mini5xxde lqfp48 v dd v ss /reset ice_dat ice_clk swd interface 1uf v dd v ss i 2 c device clk dio sda scl 4.7k v dd v ss spi device cs clk miso spiss mosi spiclk miso mosi ldo rs232 transceiver rout tin rin tout pc com port xtal1 0.1uf dvcc 4.7k dvcc dvcc note: for the spi device, the mini5x chip supply voltage must be equal to spi device working voltage. for example, when the spi flash working voltage is 3.3 v, the mini5x chip supply voltage must also be 3.3v. uart [1] rx tx
n umicro m ini51 ? de series datasheet may 22, 2014 page 50 of 70 revision 1.01 numicro m ini51 ? de series datasheet 9 mini51xxde electrica l characteristics absolute maximum ratings 9.1 symbol p arameter min m ax u nit v dd ? v ss dc power supply - 0.3 +7.0 v v in input voltage v ss - 0.3 v dd +0.3 v 1/t clcl oscillator frequency 4 24 mhz t a operating temperature - 40 +105 t st storage temperature - 55 + 150 i dd ma xim um current into v dd - 120 ma i ss maximum current out of v ss - 120 ma i io maximum current sunk by a n i/o pin - 3 5 ma maximum current sourced by a n i/o pin - 3 5 ma maximum current sunk by total i/o pins - 100 ma maximum current sourced by total i/o pins - 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lif e and reliability of the device. dc electrical characteristics 9.2 (vdd - vss = 2.5 ~ 5.5 v, ta = 25 c) symbol parameter min typ max unit test conditions v dd operation voltage 2.5 - 5.5 v v dd = 2 .5v ~ 5.5v up to 24 mhz v ss / av ss power ground - 0.3 - - v v ldo ldo output voltage 1.62 1.8 1.98 v v dd 2.5 v v bg band - gap voltage 1.20 1.24 1.28 v v dd = 2 .5v ~ 5.5v , t a = 25 c 1.18 1.24 1.32 v v dd = 2 .5v ~ 5.5v , t a = - 40 c ~105 c v dd -av dd allowed voltage difference for v dd and av dd - 0.3 0 0.3 v - i dd1 operating current normal run mode hclk = 24 mhz while(1){} executed from flash - 9.2 - ma v dd 5.5v hxt 24 mhz hirc disable all digital modules enabled
n umicro m ini51 ? de series datasheet may 22, 2014 page 51 of 70 revision 1.01 numicro m ini51 ? de series datasheet i dd2 - 7.0 - ma v dd 5.5v hxt 24 mhz hirc disabled all digital modules disabled i dd3 - 7.1 - ma v dd 3.3v hxt 24 mhz hirc disable all digital modules enabled i dd4 - 5.0 - ma v dd 3.3 v hxt 24 mhz hirc disabled all digital modules disabled i dd5 operating current normal run mode hclk =22.1184 mhz while(1){} executed from flash - 6.1 - ma v dd 5.5v hxt disabled hirc enabled all digital modules enabled i dd6 - 3.9 - ma . v dd 5.5v hxt disabled hirc enabled all digital modules disabled i dd7 - 6.0 - ma v dd 3.3v hxt disabled hirc enabled all digital modules enabled i dd8 - 3.9 - ma v dd 3.3v hxt disabled hirc enabled all digital modules disabled
n umicro m ini51 ? de series datasheet may 22, 2014 page 52 of 70 revision 1.01 numicro m ini51 ? de series datasheet i dd9 operating current normal run mode hclk = 12m h z while(1){} executed from flash - 5.5 - ma v dd 5.5 v hxt 12 mhz hirc disabled all digital modules enabled i dd10 - 4.3 - ma v dd 5.5 v hxt 12 mhz hirc disabled all digital modules disabled i dd1 1 - 3.9 - ma v dd 3.3 v hxt 12 mhz hirc disabled all digital modules enabled i dd12 - 2.8 - ma v dd 3.3 v hxt 12 mhz hirc disabled all digital modules disabled i dd13 operating current normal run mode hclk =4 mhz while(1){} executed from flash - 3.2 - ma v dd 5.5 v hxt 4 mhz hirc disabled all digital modules enabled i dd14 - 2.8 - ma v dd 5.5 v hxt 4 mhz hirc disabled all digital modules disabled i dd15 - 1.8 - ma v dd 3.3 v hxt 4 mhz hirc disabled all digital modules enabled
n umicro m ini51 ? de series datasheet may 22, 2014 page 53 of 70 revision 1.01 numicro m ini51 ? de series datasheet i dd16 - 1.4 - ma v dd 3.3 v hxt 4 mhz hirc disabled all digital modules disabled i dd17 operating current normal run mode hclk = 10 kh z while(1){} executed from flash - 225 - a v dd 5.5 v hxt disabled hirc isabled lirc enabled all digital modules enabled only enable modules which support 10 khz lirc clock source i dd18 - 225 - a v dd 5.5 v hxt disabled hirc disabled lirc enabled all digital modules disabled i dd19 - 200 - a v dd 3.3 v hxt disa led hirc disabled lirc enabled all digital modules enabled only enable modules which support 10 khz lirc clock source i dd20 - 200 - a v dd 3.3 v hxt disabled hirc disabled lirc enabled all digital modules disa led i id le 1 operating current idle mode hclk = 24 m h z - 7.1 - ma v dd 5.5v hxt 24 mhz hirc disable all digital modules enabled
n umicro m ini51 ? de series datasheet may 22, 2014 page 54 of 70 revision 1.01 numicro m ini51 ? de series datasheet i id le 2 - 4.9 - ma v dd 5.5v hxt 24 mhz hirc disabled all digital modules disabled i id le 3 - 5.1 - ma v dd 3.3v hxt 24 mhz hirc disable all digital modules enabled i id le 4 - 2.9 - ma v dd 5.5v hxt 24 mhz hirc disabled all digital modules disabled i id le 5 operating current idle mode hclk=22.1184 mhz - 4.1 - ma v dd 5.5v hxt disabled hirc enabled all digital modules enabled i id le 6 - 2.0 - ma . v dd 5.5v hxt disabled hirc enabled all digital modules disabled i id le 7 - 4.1 - ma v dd 3.3v hxt disabled hirc enabled all digital modules enabled i id le 8 - 1.9 - ma v dd 3.3v hxt disabled hirc enabled all digital modules disabled
n umicro m ini51 ? de series datasheet may 22, 2014 page 55 of 70 revision 1.01 numicro m ini51 ? de series datasheet i id le 9 operating current idle mode hclk =12 mhz - 4.4 - ma v dd 5.5 v hxt 12 mhz hirc disabled all digital modules enabled i id le 10 - 3.3 - ma v dd 5.5 v hxt 12 mhz hirc disabled all digital modules disabled i id le 11 - 2.9 - ma v dd 3.3 v hxt 12 mhz hirc disabled all digital modules enabled i id le 12 - 1.8 - ma v dd 3.3 v hxt 12 mhz hirc disabled all digital modules disabled i id le 13 operating current idle mode hclk =4 mhz - 2.9 - ma v dd 5.5 v hxt 4 mhz hirc disabled all digital modules enabled i id le 14 - 2.5 - ma v dd 5.5 v hxt 4 mhz hirc disabled all digital modules disabled i id le 15 - 1.5 - ma v dd 3.3 v hxt 4 mhz hirc disabled all digital modules enabled
n umicro m ini51 ? de series datasheet may 22, 2014 page 56 of 70 revision 1.01 numicro m ini51 ? de series datasheet i id le 16 - 1.1 - ma v dd 3.3 v hxt 4 mhz hirc disabled all digital modules disabled i id le 17 operating current idle mode at 10 khz - 225 - a v dd 5.5 v hxt disabled hirc disabled lirc enabled all digital modules enabled only enable modules which support 10 khz lirc clock source i id le 18 - 225 - a v dd 5.5 v hxt disabled hirc disabled lirc enabled all digital modules disabled i id le 19 - 200 - a v dd 3.3 v hxt disabled hirc disabled lirc enabled all digital modules enabled only enable modules which support 10 khz lirc clock source i id le 20 - 200 - a v dd 3.3 v hxt disabled hirc disabled lirc enabled all digital modules disabled i pwd1 standby current power - down mode (deep sleep mode) - 10 - a v dd = 5.5 v, all oscillators and analog blocks turned off. i pwd2 - 9 - a v dd = 3.3 v, all oscillators and analog blocks turned off. i il logic 0 i nput current p0/1/2/3/4 /5 (quasi - bidirectional m ode) - -70 -75 a v dd = 5.5 v, v in = 0v
n umicro m ini51 ? de series datasheet may 22, 2014 page 57 of 70 revision 1.01 numicro m ini51 ? de series datasheet i tl logic 1 to 0 transition current p0/1/2/3/4 /5 (quasi - bidirectional m ode) [* 3 ] - -690 -750 a v dd = 5.5 v, v in = 2.0v i lk input leakage current p0/1/2/3/4 /5 -1 - +1 a v dd = 5.5 v, 0 < v in < v dd open - drain or input only mode v il1 input low voltage p0/1/2/3/4 /5 (ttl i nput) - 0.3 - 0.8 v v dd = 4.5 v - 0.3 - 0.6 v dd = 2.5 v v ih1 input high voltage p0/1/2/3/4 /5 (ttl i nput) 2.0 - v dd + 0.3 v v dd = 5.5 v 1.5 - v dd + 0.3 v dd = 3.0 v v il3 input low voltage xt al 1[*2] 0 - 0.8 v v dd = 4.5 v 0 - 0.4 v dd = 2.5 v v ih3 input high voltage x tal 1[*2] 3.5 - v dd + 0.3 v v dd = 5.5 v 2.4 - v dd + 0.3 v dd = 3.0 v v ils negative - going t hreshold (schmitt i nput), /reset - 0.3 - 0.2v dd v - v ihs positive - going t hreshold (schmitt i nput), /reset 0.7 v dd - v dd + 0.3 v - r rst internal /resetp in p ull - up r esistor 40 150 k v dd = 2.5 v ~ 5.5v v ils negative - going t hreshold (schmitt input), p0/1/2/3/4 /5 - 0.3 - 0.3v dd v - v ihs positive - going t hreshold (schmitt input), p0/1/2/3/4 /5 0.7 v dd - v dd + 0.3 v - i sr11 source current p0/1/2/3/4 /5 (quasi - bidirectional mode) -300 -400 - a v dd = 4.5 v, v s = 2.4 v i sr12 -50 -80 - a v dd = 2.7 v, v s = 2.2 v i sr13 -40 -73 - a v dd = 2.5 v, v s = 2.0 v i sr21 source current p0/1/2/3/4 /5 (push - pull mode) -20 -26 - ma v dd = 4.5 v, v s = 2.4 v i sr22 -3 -5 - ma v dd = 2.7 v, v s = 2.2 v i sr23 - 2.5 -5 - ma v dd = 2.5 v, v s = 2.0 v i sk11 sink current p0/1/2/3/4 /5 (quasi - bidirectional , open - 10 15 - ma v dd = 4.5 v, v s = 0.45 v i sk12 6 9 - ma v dd = 2.7 v, v s = 0.45 v
n umicro m ini51 ? de series datasheet may 22, 2014 page 58 of 70 revision 1.01 numicro m ini51 ? de series datasheet i sk13 drain and push - pull mode) 5 8 - ma v dd = 2.5 v, v s = 0.45 v notes: 1. /reset pin is a schmitt trigger input. 2. xtal1 is a cmos input. 3. pins of p0, p1, p2, p3, p4 and p5 can source a transition current when they are being externally driven from 1 to 0. in the condition of vdd=5.5v, the transition current reaches its maximum value when vin approximates to 2v. ac electrical characteristics 9.3 9.3.1 external input clock t chcx 90% 10% t clch t chcl t clcx t clcl 0.3 v dd 0.7 v dd note: duty cycle is 50%. symbol p arameter m in t yp max unit test conditions t chcx clock high time 10 - - n s - t clcx clock low time 10 - - n s - t clch clock rise time 2 - 15 n s - t chcl clock fall time 2 - 15 n s - 9.3.2 external 4~24 mhz high speed crystal (hxt) symbol parameter min . typ . max unit test conditions v hx t operation voltage 2.5 - 5.5 v - t a temperature - 40 - 105 - i hxt operating c urrent - 2.5 - ma 12 mhz, v dd = 5 .5 v - 1.0 - ma 12 mhz, v dd = 3.3 v f hxt c lock f requency 4 - 24 mhz -
n umicro m ini51 ? de series datasheet may 22, 2014 page 59 of 70 revision 1.01 numicro m ini51 ? de series datasheet 9.3.3 typical crystal application circuits c rystal c1 c 2 4mhz ~ 24 mhz 10~20 pf 10~20 pf xtal1 c 1 c 2 xtal2 4~24 mhz crystal vss vss figure 9 - 1 mini5xde typical crystal application circuit 9.3.4 22.1184 mhz internal high speed rc oscillator (hirc) s ymbol parameter min typ max unit test conditions v hrc supply voltage 1.62 1.8 1.98 v - f hrc center frequency - 22. 1184 mhz - calibrated internal oscillator frequency - 1 - + 1 % t a = 25 v dd = 5 v - 2 - + 2 % t a = - 40 ~ 105 v dd =2. 5 v~ 5.5 v i hrc operating c urrent - 700 - a t a = 25 , v dd = 5 v
n umicro m ini51 ? de series datasheet may 22, 2014 page 60 of 70 revision 1.01 numicro m ini51 ? de series datasheet 9.3.5 10 khz internal low speed rc oscillator(lirc) symbol parameter min typ max unit test conditions v l rc supply v oltage 2. 5 - 5.5 v - f l rc center frequency - 10 - k hz - oscillator frequency - 1 0 - + 1 0 % v dd =2. 5 v~ 5.5 v t a = 25 - 4 0 - + 4 0 % v dd =2. 5 v~ 5.5 v t a = - 40 ~+105 -1.00 -0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 -40 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 85 90 100 110 deviation percentage % t a hirc oscillator accuracy vs. temperature max min
n umicro m ini51 ? de series datasheet may 22, 2014 page 61 of 70 revision 1.01 numicro m ini51 ? de series datasheet analog characteristics 9.4 9.4.1 10- bit saradc symbol parameter min typ max unit test c ondition - resolution - - 1 0 bit - dnl differential n onlinearity e rror - - 1~1.5 - 1~+2.5 lsb - inl integral n onlinearity e rror - 1 2 lsb - e o offset e rror - 1 2 lsb - e g gain e rror (transfer g ain) - - 1 - 3 lsb - e a absolute e rror - 3 4 lsb - - monotonic guaranteed - - f adc adc c lock f requency - - 4.2 mhz a v dd = 4.5~5. 5 v - - 2.8 a v dd = 2.5~5.5 v f s sample r ate (f adc /t conv ) - - 300 ksps a v dd = 4. 5 ~5.5 v - - 200 ksps a v dd = 2. 5 ~5.5 v t acq acquisition t ime (sample s tage) n+1 1/f adc n is sampling counter, n=0,1,2, 4,8, 16,32, 4, 128, 256,1024 t c onv total c onversion t ime n+14 1/f adc a v dd supply v oltage 2.5 - 5.5 v - i dda supply c urrent (avg.) - 600 - a a v dd = 5.5 v v in analog input v oltage 0 - a v dd v - c in input c apacitance - 3.2 - pf - r in input load - 6 - k - note: adc voltage reference is same with a v dd
n umicro m ini51 ? de series datasheet may 22, 2014 page 62 of 70 revision 1.01 numicro m ini51 ? de series datasheet 1 2 3 4 5 6 1023 1022 7 1021 1020 ideal transfer curve actual transfer curve offset error e o analog input voltage (lsb) 1023 adc output code offset error e o gain error e g e f (full scale error) = e o + e g dnl 1 lsb 9.4.2 ldo & power management symbol p a rameter m in typ max unit test condition v dd dc power supply 2. 5 - 5.5 v - v ldo output voltage 1.62 1.8 1.98 v - t a temperature - 40 25 105 notes: 1. it is recommended a 0.1f bypass capacitor is connected between v dd and the closest v ss pin of the device. 9.4.3 low voltage reset s ymbol parameter min typ max unit test condition av dd supply voltage 0 - 5.5 v -
n umicro m ini51 ? de series datasheet may 22, 2014 page 63 of 70 revision 1.01 numicro m ini51 ? de series datasheet t a temperature - 40 25 105 - i lvr quiescent current - 1 5 a a v dd =5.5v v lvr threshold v oltage 1. 90 2.0 0 2. 10 v t a =25 1.70 1.90 2.05 v t a = - 40 2.00 2.20 2.45 v t a = 105 9.4.4 brown - out detector symbol parameter min typ max unit test condition av dd supply voltage 0 - 5.5 v - t a temperature - 40 25 105 - i bod quiescent c urrent - - 1 40 $ av dd =5.5v v bod brown - o ut detector (falling edge) 4. 2 4. 38 4. 55 v bod_vl [1:0]=11 3. 5 3. 68 3. 85 v bod_vl [1:0]=10 2. 5 2. 68 2. 85 v bod_vl [1:0]=01 2 .0 2. 18 2. 35 v bod_vl [1:0]=00 v bod brown - o ut detector (rising edge) 4. 3 4. 52 4. 75 v bod_vl [1:0]=11 3. 5 3. 8 4.05 v bod_vl [1:0]=10 2. 5 2. 77 3.05 v bod_vl [1:0]=01 2 .0 2. 25 2. 55 v bod_vl [1:0]=00 9.4.5 power - on reset symbol parameter min typ max unit test condition t a temperature - 40 25 105 - v por reset v oltage 1.6 2 2.4 v - v por v dd start voltage to ensu r e power - on reset - - 100 mv rr vdd v dd raising rate to ensu r e power - on reset 0.025 - - v/ms t por minimum time for v dd stays at vpor to ensu r e power - on reset 0.5 - - ms
n umicro m ini51 ? de series datasheet may 22, 2014 page 64 of 70 revision 1.01 numicro m ini51 ? de series datasheet t por rr vdd v por v dd time figure 9 - 2 power - up ramp condition 9.4.6 comparator symbol p arameter m in typ m ax u nit test condition v cmp supply voltage 2.5 - 5.5 v t a temperature - 40 25 105 - i cmp operation c urrent - 40 80 a a v dd = 5 v v of f input o ffset v oltage 10 20 mv - v sw output s wing 0.1 - a v dd - 0.1 v - v com input c ommon m ode r ange 0.1 - a v dd ? 0.1 v - - dc g ain 40 70 - db - t p gd propagation d elay - 200 - ns v c o m =1.2 v , v diff =0.1 v v hy s hysteresis - 30 60 mv v c o m =1.2 v t s tb stable time - - 1 s
n umicro m ini51 ? de series datasheet may 22, 2014 page 65 of 70 revision 1.01 numicro m ini51 ? de series datasheet flash dc electrical characteristics 9.5 symbol parameter min typ max unit test condition v fla [2] supply voltage 1.62 1.8 1.98 v n e nd ur endurance 20,000 - - cycles [1] t ret data retention 10 - - year t a = 85 t erase page erase time - 20 - ms t prog program time - 60 - us i dd1 read current - 6 - ma i dd2 program current - 8 - ma i dd3 erase current - 12 - ma notes: 1. number of program/erase cycles. 2. v fla is source from chip ldo output voltage. 3. guaranteed by design, not test in production.
n umicro m ini51 ? de series datasheet may 22, 2014 page 66 of 70 revision 1.01 numicro m ini51 ? de series datasheet 10 package dimension s 48- p in lqfp 10.1
n umicro m ini51 ? de series datasheet may 22, 2014 page 67 of 70 revision 1.01 numicro m ini51 ? de series datasheet 33- p in qfn (4 mm x 4 mm ) 10.2
n umicro m ini51 ? de series datasheet may 22, 2014 page 68 of 70 revision 1.01 numicro m ini51 ? de series datasheet 33- p in qfn (5 mm x 5 mm ) 10.3
n umicro m ini51 ? de series datasheet may 22, 2014 page 69 of 70 revision 1.01 numicro m ini51 ? de series datasheet 20- p in tssop 10.4
n umicro m ini51 ? de series datasheet may 22, 2014 page 70 of 70 revision 1.01 numicro m ini51 ? de series datasheet 11 revision history revision date description 1.00 oct . 18 , 2013 preliminary version 1.01 may 20, 2014 supported the mini54fhc for numicro mini51 series. important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed , ?insecure usage?. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instrumen ts, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insec ure usage shall be made at customer?s risk, and in the event that third parties lay claims to nuvoton as a result of customer?s insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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